Low Voltage Mixed-Mode Fuzzy Logic Accelerator - Ranasinghe, Anuradha (fi=Turun yliopisto|en=University of Turku|, 2018)
The escalating performance demands of context-aware applications have recently motivated the use of hardware accelerators over their traditional homogeneous architectures. Despite having advanced CMOS technology nodes being a plus factor for the implementation of hardware accelerators, operating them within a reasonable power budget is a daunting task. The utilization of Near-Threshold Computing with Mixed-Mode circuit techniques seems to be a tempting solution to address these requirements. The adaption of natural computing techniques such as Fuzzy Logic allows the context-aware applications to mimic anthropomorphic behavior for intelligent control. Traditionally the realization of fuzzy logic as a computational platform was accomplished by employing digital processors or FPGAs. The main drawback of this approach is their inherent area and power hungry nature. Alternatively the Mixed-Mode approach can be used to realize an area and energy efficient solution while preserving the functional accuracy of the design. This thesis presents the implementation details of current-mode design blocks for a Mixed-Mode hardware fuzzy logic accelerator. Presented data converters and fuzzy logic cores are intended to be integrated into a single system enabling its operation as a standalone fuzzy processor. The fuzzy logic cores are composed of a novel fuzzifier circuit, a Min-Max operator and an analog divider circuit. The current-mode data converters are comprised of 4-bit DACs, a 4-bit SAR ADC and a current comparator. Proposed implementation strategies were simulated and verified on transistor level with 130 nm digital CMOS technology at 0.5V Near-Threshold supply voltage using Cadence Spectre simulation environment. Although the Near-Threshold operation is accompanied by a dramatic drop in performance, the circuit functionality was preserved with aid of circuit level techniques. Requirements of low power consumption, area efficiency and maximum programmability of the membership functions have been met. A prototype chip was also implemented for the proposed novel fuzzifier circuit along with auxiliary circuit test structures.