Research and Design of a high-efficiency Class-F Power Amplifier - Mengjia, Sun (fi=Turun yliopisto|en=University of Turku|, 2018)
Power amplifiers are important parts in communication systems. They are often used at the end of the transmitter and the front of the receiver. Research on power amplifiers is also developing fast. Expect for linear power amplifiers, switch-mode power amplifiers have been popular among the high-efficiency power amplifiers designers. Basic theories and performance parameters of power amplifiers, as well as classification of the amplifiers are introduced in this thesis. Then the research background and basic structure of Class-F power amplifiers are introduced in detail. Class-F power amplifiers have the advantage of high efficiency, because its ideal drain output voltage and current are square and half-sine waveforms with a phase difference of 180º. In this way, the overlap area is cut down and the power consumed by the transistor is reduced. This thesis uses the Advanced Design System (ADS) software to get the best direct current quiescent operation point of the transistor, and then get the impedance of the transistor at different harmonics through the Load-pull and Source-pull template. Based on the data collected, a harmonic control circuit is designed with compensating of the parasites to raise the efficiency of the amplifier. After getting the final input and output matching network, we finally get the schematic of the designed Class-F power amplifier. According to the optimized schematic, the simulation result is when the input power is 33 dBm, the output power is 41.64 dBm at the frequency of 2.45 GHz. And the power added efficiency is 81.75%, which achieves the design goal. Considering second and third harmonics needed to be controlled, the whole size of the network will be large, over 10 cm in length. So research about design of a compact Class-F power amplifier is done. Associated with the low-pass filter structure, simplified real frequency technique (SRFT) is used to calculate the parameters of the matching network, which can achieve of the aimed value of the transducer power gain (TPG). Such a method can match the impedance well, as well as control the harmonics effectively. The simulation result of the final optimized compact Class-F power amplifier is when the input power is 33 dBm, the output power is 42 dBm at the frequency of 2.45 GHz, with a power added efficiency (PAE) of 80.51%. The design achieves the design goal and effectively cut the size of the whole circuit. The final size of the circuit is 5 cm x 6 cm. Then a co-simulation of layout and schematic is done in ADS. Compared with schematic simulation, the result of co-simulation is more accurate and help reduce some possible errors before fabricating. The result of layout co-simulation can reach a PAE of 64.23%. Keyword: High-efficiency, Class-F power amplifier, SRFT