Run-time Power Management for Heterogeneous Many-Core Systems in the Dark Silicon Era
Ghalavand, Mohammadjavad (2017-08-15)
Run-time Power Management for Heterogeneous Many-Core Systems in the Dark Silicon Era
Ghalavand, Mohammadjavad
(15.08.2017)
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The inactive part of a chip, termed as Dark Silicon, is extending rapidly by introducing new technology nodes due to thermal design power (TDP) constraints. These power constraints actually prevent us taking advantage from the increasing number of transistors provided by new technology generations. To solve this issue, heterogeneous computing and dynamic power management strategies are the right approaches to proceed.
For this reason, as a contribution of this thesis, dynamic mapping and power management approaches are provided for shared-memory many-core systems through introducing a power management unit that comprises of two modules, namely runtime mapping unit (RMU) and power controller unit. RMU component is able to map applications’ threads into the targeted group of cores. Power controller unit adjusts the power consumption of the system, considering TDP and utilizing DVFS technique as well as application’s threads migration from Big cores to Small ones or vice versa. An algorithm is also proposed for hierarchical power management through which not only power management actuators such as DVFS can be manipulated in an optimal manner but also the mapping scheme of threads to asymmetric many-cores are determined at runtime, improving both performance and energy efficiency.
To evaluate our proposed design, a NoC-based many-core system comprising of 64 Kingscross cores (the first 32 cores are Big, and the rest are Small) is provided and simulated by Sniper simulator. The obtained results of running a Splash-2 benchmark, fft, show that throughout the frequency range, Big cores have a better performance than Small cores, even though they are more power hungry. With per-core power gating (PCPG) technique in use, the minimum energy consumption occurs with cases of application running sequentially no matter being run on Big or Small cores. Surprisingly, Big cores are more energy efficient than Small ones. Furthermore, the optimal frequencies that provide lower values of both energy consumption and execution time are somewhere in the middle of energy consumption - execution time graphs at 1000 and 1500 MHz for Big and Small cores, respectively. Additionally, the power trace and throughput graphs show that employing both DVFS and migration techniques concurrently is more effective in terms of power controlling and obtaining better performance results compared to when they are used individually.
For this reason, as a contribution of this thesis, dynamic mapping and power management approaches are provided for shared-memory many-core systems through introducing a power management unit that comprises of two modules, namely runtime mapping unit (RMU) and power controller unit. RMU component is able to map applications’ threads into the targeted group of cores. Power controller unit adjusts the power consumption of the system, considering TDP and utilizing DVFS technique as well as application’s threads migration from Big cores to Small ones or vice versa. An algorithm is also proposed for hierarchical power management through which not only power management actuators such as DVFS can be manipulated in an optimal manner but also the mapping scheme of threads to asymmetric many-cores are determined at runtime, improving both performance and energy efficiency.
To evaluate our proposed design, a NoC-based many-core system comprising of 64 Kingscross cores (the first 32 cores are Big, and the rest are Small) is provided and simulated by Sniper simulator. The obtained results of running a Splash-2 benchmark, fft, show that throughout the frequency range, Big cores have a better performance than Small cores, even though they are more power hungry. With per-core power gating (PCPG) technique in use, the minimum energy consumption occurs with cases of application running sequentially no matter being run on Big or Small cores. Surprisingly, Big cores are more energy efficient than Small ones. Furthermore, the optimal frequencies that provide lower values of both energy consumption and execution time are somewhere in the middle of energy consumption - execution time graphs at 1000 and 1500 MHz for Big and Small cores, respectively. Additionally, the power trace and throughput graphs show that employing both DVFS and migration techniques concurrently is more effective in terms of power controlling and obtaining better performance results compared to when they are used individually.