Study of soft error in System-on-Chip memories and mitigation methods
Nguyen, Duc (2021-06-28)
Study of soft error in System-on-Chip memories and mitigation methods
(28.06.2021)
Julkaisu on tekijänoikeussäännösten alainen. Teosta voi lukea ja tulostaa henkilökohtaista käyttöä varten. Käyttö kaupallisiin tarkoituksiin on kielletty.
suljettu
Julkaisun pysyvä osoite on:
https://urn.fi/URN:NBN:fi-fe2021070240978
https://urn.fi/URN:NBN:fi-fe2021070240978
Tiivistelmä
Soft error in static random-access memory (SRAM) caused by radiation has been shown to be one of the causes for major performance degradation or catastrophic failures in modern System-on-Chips (SoC). The effect of radiation in SoC is more pronounced in space or at higher altitude in the atmosphere of the earth but it is also detected at sea level. Based on literature, we find that newer technology, even with their geometries of the devices being scaled down aggressively, plays a key role in reducing the soft error rate. Furthermore, the new FinFET technology offers more reduction than Planar FET technology in terms of soft error rate. On the other hand, the soft error rate is negatively affected by reducing operating voltage in order to lower power consumption. However, the rate that soft error occurs is increasing in general because of the fact that more and more SRAM cells are used in newer SoC.
This thesis discusses the use of error correction code (ECC) as countermeasure against soft errors in SRAM and give insights about what parameters to be considered in order to optimize a SRAM ECC design. SRAM memory with ECC based on Hamming code is implemented in VHDL and compared with a proprietary ECC IP.
By comparing the synthesis results, we can observe certain trends and trade off between different parameters. Depending on the target clock speed, silicon area is increased by 15-70% when ECC is added to the memory. Memories with ECC are still fast enough for most practical cases even though the maximum frequency drops by 60-70% when ECC is added to memory and thus there is a trade off between data width, speed, and area. Namely, it is possible to achieve higher clock speed by using narrower data width, but the disadvantage is the larger area penalty. Conversely, even though ECC memory with wider data width has lower clock speed, it also has lower overhead in terms of area. Finally, synthesis results show a marginally better result of Vendor1 ECC IP compared with Hamming ECC. There is a catch, however, that is the IP licensing cost, the in-house Hamming ECC is free within Nokia while one may need to pay to license the use of ECC IP from Vendor1 commercially.
This thesis discusses the use of error correction code (ECC) as countermeasure against soft errors in SRAM and give insights about what parameters to be considered in order to optimize a SRAM ECC design. SRAM memory with ECC based on Hamming code is implemented in VHDL and compared with a proprietary ECC IP.
By comparing the synthesis results, we can observe certain trends and trade off between different parameters. Depending on the target clock speed, silicon area is increased by 15-70% when ECC is added to the memory. Memories with ECC are still fast enough for most practical cases even though the maximum frequency drops by 60-70% when ECC is added to memory and thus there is a trade off between data width, speed, and area. Namely, it is possible to achieve higher clock speed by using narrower data width, but the disadvantage is the larger area penalty. Conversely, even though ECC memory with wider data width has lower clock speed, it also has lower overhead in terms of area. Finally, synthesis results show a marginally better result of Vendor1 ECC IP compared with Hamming ECC. There is a catch, however, that is the IP licensing cost, the in-house Hamming ECC is free within Nokia while one may need to pay to license the use of ECC IP from Vendor1 commercially.