Evaluation of Verification practices for digital design
Arponen, Joona (2022-05-11)
Evaluation of Verification practices for digital design
(11.05.2022)
Julkaisu on tekijänoikeussäännösten alainen. Teosta voi lukea ja tulostaa henkilökohtaista käyttöä varten. Käyttö kaupallisiin tarkoituksiin on kielletty.
suljettu
Julkaisun pysyvä osoite on:
https://urn.fi/URN:NBN:fi-fe2022062148369
https://urn.fi/URN:NBN:fi-fe2022062148369
Tiivistelmä
The development process of digital integrated circuits is increasingly needing resources for design verification development effort. Verification directly impacts and indicates on the quality of the design and it is often the most critical challenge project faces, thus expanding effort. It is difficult to estimate how comprehensive the verification is and what techniques should be applied and how much. Exhaustively comprehensive verification might not be realistic. Different methodologies and techniques demand wide experience and purpose-driven approach but the overall problems in design verification stay the same with limited number of computing elements in design logic. Finding the right technique for right logic element for verification is the goal that not only affects the project workload, but also ensures the quality in design.
The verification techniques are introduced and implemented in a design development. They are evaluated during the process of the implementation for finding possible limitations of the technique and possible niche to be applied most effectively.
The verification during the process did not resurface any critical differences between FPGA or ASIC projects, most of the differences related to FPGA-projects dependencies with vendor IP. The techniques tested were UVM-methodology -based stimulus-based verification, ABV, CDC, RDC and other static structural checks. The verification techniques and methodologies were divided into three (3) different types based on the fundamentals of the technique, Simulation, formal and static verification.
It was found that control logic type of structure as in FSM, handshake protocol interfaces, memory structures could be verified with decent effort exhaustively with formal showing niche there. Simulation on the other hand is providing good coverage and clear niche in verifying arithmetic operations and data manipulation operations in general, while having decent effectiveness in protocol interfaces and memories, being usable in control logic as well, thus not having as exhaustive verification as formal. Therefore simulation in generally fit for all, but not as effective everywhere. Static in general is easy to implement to verification, but it is not that effective, since the tools used are meant for specific use-cases making it not that effective, but in niche cases, such as initialization check and LINT in highly effective. Findings were as expected in some parts. Static and formal tools have been becoming more and more effective that was seen in testing. Also, FPGA and ASIC verification have less differences than expected. Wider verification practices in project should be utilized more and these should be implemented especially in those niche structures of design. This would decrease the needed resources and project time as well as provide more quality products.
The verification techniques are introduced and implemented in a design development. They are evaluated during the process of the implementation for finding possible limitations of the technique and possible niche to be applied most effectively.
The verification during the process did not resurface any critical differences between FPGA or ASIC projects, most of the differences related to FPGA-projects dependencies with vendor IP. The techniques tested were UVM-methodology -based stimulus-based verification, ABV, CDC, RDC and other static structural checks. The verification techniques and methodologies were divided into three (3) different types based on the fundamentals of the technique, Simulation, formal and static verification.
It was found that control logic type of structure as in FSM, handshake protocol interfaces, memory structures could be verified with decent effort exhaustively with formal showing niche there. Simulation on the other hand is providing good coverage and clear niche in verifying arithmetic operations and data manipulation operations in general, while having decent effectiveness in protocol interfaces and memories, being usable in control logic as well, thus not having as exhaustive verification as formal. Therefore simulation in generally fit for all, but not as effective everywhere. Static in general is easy to implement to verification, but it is not that effective, since the tools used are meant for specific use-cases making it not that effective, but in niche cases, such as initialization check and LINT in highly effective. Findings were as expected in some parts. Static and formal tools have been becoming more and more effective that was seen in testing. Also, FPGA and ASIC verification have less differences than expected. Wider verification practices in project should be utilized more and these should be implemented especially in those niche structures of design. This would decrease the needed resources and project time as well as provide more quality products.