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Analysing and Modelling the On-chip Traffic of Parallel Applications

Thomas Xu; Jonne Pohjankukka; Ville Leppänen

Analysing and Modelling the On-chip Traffic of Parallel Applications

Thomas Xu
Jonne Pohjankukka
Ville Leppänen
Katso/Avaa
Final draft (673.8Kb)
Lataukset: 

doi:10.1109/SEAA.2016.25
URI
http://ieeexplore.ieee.org/document/7592808/
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Julkaisun pysyvä osoite on:
https://urn.fi/URN:NBN:fi-fe2021042716221
Tiivistelmä

In this paper, we investigate the traffic characteristics of parallel
and high performance computing applications. Parallel applications that
utilize multiple processing cores are widespread nowadays due to the
trend of multicore processors. However the design paradigm of
traditional sequential execution and concurrent execution can vary
significantly. Therefore the estimation and prediction approaches used
in conventional software can be limited for parallel applications. The
communication among different nodes in a multicore system should be
analysed and categorized in order to improve the accuracy of system
simulation. We study several parallel applications running on a full
system simulation environment. The communication traces among different
nodes are collected and analysed. We discuss the detailed
characteristics of these applications. The applications are grouped into
different categories depending on several parallel programming
paradigms. We apply power-law model with maximum likelihood estimation,
Gaussian mixture model, as well as the polynomial model for fitting the
trace data. A generic synthetic traffic model is proposed based on the
results. Experiments show the proposed model can be used to evaluate the
performance of parallel systems more accurately than by other synthetic
traffic models.

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