A robust ultra-low voltage CPU utilizing timing-error prevention
Markus Hiienkari; Jukka Teittinen; Arto Rantala; Lauri Koskinen; Matthew Turnquist; Matti Sopanen; Jani Mäkipää; Mikko Kaltiokallio
https://urn.fi/URN:NBN:fi-fe2021042715538
Tiivistelmä
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.
Kokoelmat
- Rinnakkaistallenteet [19207]