Implementation of Covariance Matrix for 5G New Radio

Abstract

The fifth-generation communication technology or 5G has been envisioned to provide 100 times faster speed with 10 times reduced latency to its users, when compared to the Fourth Generation Long Term Evolution (4G-LTE) technology. The users may not only be humans rather machines and other "things" which could communicate with the surroundings. Such performance expectations from the 5G technology have been based on techniques like Massive MIMO (Multiple Input Multiple Output) and Beamforming. Massive MIMO is a step forward in the Multi-User MIMO technology which employs multiple antennas for communication. Massive MIMO involves using a large number of antennas arrays along with the application of beamforming to construct user-specific beams for communication between the base station and the users. This enhances the spectral efficiency, data rate and the number of serviced users is increased significantly. Beamforming is performed based on the beamforming weights which configures the individual antennas in a way that a concentrated beam can be formed in the desired direction. The weights may be computed using the Covariance Matrix estimated from the Sound Reference Signal(SRS) based Channel Estimation. The SRS is transmitted by the User Equipment (UE) to the gNodeB (gNB) and it can be used by the gNB to estimate the Channel State Information (CSI). The CSI and the beamforming weights computation should be completed within a part of the small time span when the user is relatively still (in microseconds) to take the advantage of beamforming. In order to meet these time-critical requirements, a fast and efficient system is necessary which could not only handle the functional complexity but successfully meet the latency requirements as well. This criterion can be fulfilled by hardware design (using Field Programmable Gate Array) due to its advanced computational capabilities and speed. The modern FPGA’s incorporate advanced architectural features which allow the Hardware Description Language (HDL) design to be highly optimised in terms of achievable clock frequency and efficiency. The performance depends on the design implementation in order to enable the efficient use of specialised features of the FPGA architecture such as the Digital Signal Processor blocks. This thesis focuses on researching and understanding the covariance matrix computation and transforming the logically optimal formula into a hardware design on an Intel Stratix 10 FPGA. The design approach focuses on reducing resource usage and boosting the speed of the design (fmax). This optimisation process has been recorded in six test cases and a detailed analysis has been conducted to explain the architectural properties and reason behind the performance results.