On-die CMOS temperature sensors

Abstract

Temperature changes can have an impact on the reliability and functioning of sensitive integrated circuits. In this thesis an analog DTMOS transistor temperature was designed and laid out in 22 nm CMOS fabrication process using Cadence Virtuoso electrical design automation suite. The design was verifed and validated using Cadence Spectre electrical simulation software and the simulation results were analyzed and compared to previous sensor designs. The new design was found to be less power hungry but slightly less accurate than the original design. The new design also showed a signifcant improvement in operating voltage resilience compared to a previous design used at LG Electronics Finland Lab Oy. Over all the design goals were met and the sensor is ready to be added to be a part of a future integrated circuit.