Silicon synapse designs for VLSI neuromorphic platform
| dc.contributor.author | Nguyen Duc Bui Phong | |
| dc.contributor.author | Masoud Daneshtalab | |
| dc.contributor.author | Sergei Dytckov | |
| dc.contributor.author | Juha Plosila | |
| dc.contributor.author | Hannu Tenhunen | |
| dc.contributor.organization | fi=matemaattis-luonnontieteellinen tiedekunta|en=Faculty of Science| | |
| dc.contributor.organization | fi=ohjelmistotekniikka|en=Software Engineering| | |
| dc.contributor.organization | fi=sulautettu elektroniikka|en=Embedded Electronics| | |
| dc.contributor.organization-code | 1.2.246.10.2458963.20.20754768032 | |
| dc.contributor.organization-code | 1.2.246.10.2458963.20.36798383026 | |
| dc.contributor.organization-code | 2606802 | |
| dc.contributor.organization-code | 2606804 | |
| dc.converis.publication-id | 2101820 | |
| dc.converis.url | https://research.utu.fi/converis/portal/Publication/2101820 | |
| dc.date.accessioned | 2022-10-27T12:15:24Z | |
| dc.date.available | 2022-10-27T12:15:24Z | |
| dc.description.abstract | <div> Analog silicon neurons were proven to be a promising solution for VLSI neuromorphic platform to implement massively scalable computing systems. They possess the advantages of consuming less power and silicon area than digitally designed neurons. This paper compares the differences in power and area consumption between two methods of synapse design for analog neuron models: time-based modulation and current-based modulation. The obtained results demonstrate that under the same technology process (ST CMOS 65nm), the neuron that uses time-based modulation consumes less power (almost six times) and silicon area (about thirty times) but higher energy (twelve times) than that of the current-based modulation</div> | |
| dc.format.pagerange | 1 | |
| dc.format.pagerange | 6 | |
| dc.identifier.isbn | 978-1-4799-5443-8 | |
| dc.identifier.olddbid | 174259 | |
| dc.identifier.oldhandle | 10024/157353 | |
| dc.identifier.uri | https://www.utupub.fi/handle/11111/34055 | |
| dc.identifier.url | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7004745 | |
| dc.identifier.urn | URN:NBN:fi-fe2021042714466 | |
| dc.language.iso | en | |
| dc.okm.affiliatedauthor | Dytckov, Sergei | |
| dc.okm.affiliatedauthor | Daneshtalab, Masoud | |
| dc.okm.affiliatedauthor | Plosila, Juha | |
| dc.okm.affiliatedauthor | Tenhunen, Hannu | |
| dc.okm.discipline | 213 Electronic, automation and communications engineering, electronics | en_GB |
| dc.okm.discipline | 213 Sähkö-, automaatio- ja tietoliikennetekniikka, elektroniikka | fi_FI |
| dc.okm.internationalcopublication | international co-publication | |
| dc.okm.internationality | International publication | |
| dc.okm.type | A4 Conference Article | |
| dc.relation.conference | Nordic microelectronics conference | |
| dc.relation.doi | 10.1109/NORCHIP.2014.7004745 | |
| dc.source.identifier | https://www.utupub.fi/handle/10024/157353 | |
| dc.title | Silicon synapse designs for VLSI neuromorphic platform | |
| dc.title.book | 32nd NORCHIP Conference 27-28 October 2014, Tampere, Finland | |
| dc.year.issued | 2014 |
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