Supporting Concurrent Memory Access in TCF-aware Processor Architectures

Abstract

<p>The Thick Control Flow (TCF) model packs together selfsimilar<br />computations to simplify parallel programming and to eliminate<br />redundant usage of associated software and hardware resources.<br />While there are processor architectures supporting native execution<br />of programs written for the model, none of them support concurrent<br />memory access that can speed up execution of many algorithms by a<br />logarithmic factor. In this paper, we propose an architectural solution<br />implementing concurrent memory access for TCF-aware processors.<br />The solution is based on bounded size step caches and two-phase<br />structure of the TCF-aware processors. Step caches capture and hold<br />the references made during the on-going step of an execution that<br />are independent by the definition of TCF execution and therefore<br />avoid coherence problems. The 2-phase structure reduces some concurrent<br />accesses to a frontend operation followed by broadcast in the<br />spreading network. According to our evaluation, a concurrent memory<br />access-aware B-backend unit TCF processor executes certain algorithms<br />up to B times faster than the baseline TCF processor.<br /></p>