Development of the simulation of the 5G New Radio Uplink Channels for testing the layer one of a 5G New Radio modem chip

Abstract

The 5G technology is a step forward in the telecommunication industry, and it will provide improvements and new features to the current 4G standard such as higher speed in data transmissions, energy efficiency, massive Multiple Input Multiple Output and performance adaptation to different devices.

Because of the 5G disruptive nature, MediaTek wants to give this technology to its customers and it intends to do so by developing a 5G New Radio modem. The main challenge of developing a 5G New Radio modem is that it must be based on the Third Generation Partnership Project specifications that are written while the modem chip is developed. As a result, the development of a 5G modem must be fast to quickly adapt to new Third Generation Partnership Project features while coping with competition. Nonetheless, because of the short developing time available for developing the 5G New Radio modem chip, the debugging has to be done during the development phase and it has to be time efficient to quickly give feedback to the development of the 5G New Radio modem chip.

This thesis describes the 5G New Radio Uplink Channels simulation that has been developed to test the software of the modem chip, to test the interface between the hardware and the software and finally to check the correct behavior of the hardware. The simulation has then been tested in a pure software environment and in a Register-Transfer Level environment. The Register-Transfer Level simulation is much slower than the pure software simulation. To speed up the debugging of the software, and quickly give feedback to the development of the 5G New Radio modem chip, in the pure software environment a register − check function was implemented. The register − check function can detect the modem registers mismatches and in turn detects the software bugs in the software environment before running the Register-Transfer Level simulation. This strategy has been proven to be successful because it has identified almost all the software bugs before running the Register-Transfer Level simulation, saving time during the software debugging phase.