Formal Power Analysis of Systems-on-Chip

dc.contributorMatemaattis-luonnontieteellinen tiedekunta / Faculty of Mathematics and Natural Sciences, Department of Information Technology-
dc.contributor.authorTuominen, Johanna
dc.contributor.departmentfi=Tulevaisuuden teknologioiden laitos|en=Department of Future Technologies|
dc.contributor.facultyfi=Matemaattis-luonnontieteellinen tiedekunta|en=Faculty of Mathematics and Natural Sciences|-
dc.date.accessioned2009-11-17T07:34:30Z
dc.date.available2009-11-17T07:34:30Z
dc.date.issued2009-12-07
dc.description.abstractThe design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.en
dc.description.accessibilityfeatureei tietoa saavutettavuudesta
dc.description.notificationSiirretty Doriasta
dc.format.contentfulltext
dc.identifierISBN 978-952-12-2357-0en
dc.identifier.olddbid53011
dc.identifier.oldhandle10024/50410
dc.identifier.urihttps://www.utupub.fi/handle/11111/28850
dc.language.isoengeng
dc.publisherTurku Centre for Computer Science
dc.relation.ispartofseriesTUCS Dissertations
dc.relation.issn1239-1883
dc.relation.numberinseries121-
dc.source.identifierhttps://www.utupub.fi/handle/10024/50410
dc.titleFormal Power Analysis of Systems-on-Chipen
dc.type.ontasotfi=Monografiaväitöskirja|en=Doctoral dissertation (monograph)|en

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